blob: 7b9188c82425b8b742d02ec1b2306ca34cff66b1 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
|
import cpu.Registers
import io.kotlintest.shouldBe
import io.kotlintest.shouldThrow
import io.kotlintest.specs.StringSpec
import java.lang.IllegalArgumentException
class RegisterTest : StringSpec({
"Test 16-Bit accessors" {
val reg = Registers()
reg.AF = 0xF83C
reg.AF shouldBe 0xF83C
reg.A shouldBe 0xF8
reg.F shouldBe 0x3C
reg.BC = 0xF83C
reg.BC shouldBe 0xF83C
reg.B shouldBe 0xF8
reg.C shouldBe 0x3C
reg.DE = 0xF83C
reg.DE shouldBe 0xF83C
reg.D shouldBe 0xF8
reg.E shouldBe 0x3C
reg.HL = 0xF83C
reg.HL shouldBe 0xF83C
reg.H shouldBe 0xF8
reg.L shouldBe 0x3C
}
"Test 8-Bit register validation" {
val reg = Registers()
shouldThrow<IllegalArgumentException> {
reg.A = 0xFFFF
Any()
}
shouldThrow<IllegalArgumentException> {
reg.F = 0xFFFF
Any()
}
shouldThrow<IllegalArgumentException> {
reg.B = 0xFFFF
Any()
}
shouldThrow<IllegalArgumentException> {
reg.C = 0xFFFF
Any()
}
shouldThrow<IllegalArgumentException> {
reg.D = 0xFFFF
Any()
}
shouldThrow<IllegalArgumentException> {
reg.E = 0xFFFF
Any()
}
shouldThrow<IllegalArgumentException> {
reg.H = 0xFFFF
Any()
}
shouldThrow<IllegalArgumentException> {
reg.L = 0xFFFF
Any()
}
}
"Test 16-Bit register validation" {
val reg = Registers()
shouldThrow<IllegalArgumentException> {
reg.AF = 0xFFFFFF
Any()
}
shouldThrow<IllegalArgumentException> {
reg.BC = 0xFFFFFF
Any()
}
shouldThrow<IllegalArgumentException> {
reg.DE = 0xFFFFFF
Any()
}
shouldThrow<IllegalArgumentException> {
reg.HL = 0xFFFFFF
Any()
}
shouldThrow<IllegalArgumentException> {
reg.SP = 0xFFFFFF
Any()
}
shouldThrow<IllegalArgumentException> {
reg.PC = 0xFFFFFF
Any()
}
}
"Test registers" {
val reg = Registers()
reg.A = 0xA0
reg.A shouldBe 0xA0
reg.F = 0xA1
reg.F shouldBe 0xA1
reg.B = 0xA2
reg.B shouldBe 0xA2
reg.C = 0xA3
reg.C shouldBe 0xA3
reg.D = 0xA4
reg.D shouldBe 0xA4
reg.E = 0xA5
reg.E shouldBe 0xA5
reg.H = 0xA6
reg.H shouldBe 0xA6
reg.L = 0xA7
reg.L shouldBe 0xA7
reg.SP = 0xAAFE
reg.SP shouldBe 0xAAFE
reg.PC = 0xAAFE
reg.PC shouldBe 0xAAFE
}
})
|