3 files changed, 24 insertions, 1 deletions
diff --git a/src/main/kotlin/cpu/Cpu.kt b/src/main/kotlin/cpu/Cpu.kt
index 7ea34a4..e755a08 100644
--- a/src/main/kotlin/cpu/Cpu.kt
+++ b/src/main/kotlin/cpu/Cpu.kt
@@ -1,5 +1,6 @@
 package cpu
 
+import cpu.opcodes.loads16Bit
 import cpu.opcodes.loads8Bit
 import ram.Ram
 
@@ -12,6 +13,7 @@ class Cpu {
   init {
     val commandGroups: MutableMap<Int, Operation> = mutableMapOf()
     commandGroups.putAll(loads8Bit)
+    commandGroups.putAll(loads16Bit)
     opcodes = commandGroups.toMap()
   }
 
diff --git a/src/main/kotlin/cpu/Registers.kt b/src/main/kotlin/cpu/Registers.kt
index 5f45e87..70c7f06 100644
--- a/src/main/kotlin/cpu/Registers.kt
+++ b/src/main/kotlin/cpu/Registers.kt
@@ -123,4 +123,12 @@ class Registers {
     }
   }
 
+  fun getAndIncrementSP(): Int {
+    val currentSP = SP
+    if(SP < 0xFFFF) {
+      SP++
+    }
+    return currentSP
+  }
+
 }
 \ No newline at end of file
diff --git a/src/main/kotlin/cpu/opcodes/Loads16Bit.kt b/src/main/kotlin/cpu/opcodes/Loads16Bit.kt
index 6c915cf..671a02d 100644
--- a/src/main/kotlin/cpu/opcodes/Loads16Bit.kt
+++ b/src/main/kotlin/cpu/opcodes/Loads16Bit.kt
@@ -1,6 +1,8 @@
 package cpu.opcodes
 
 import cpu.Operation
+import cpu.Registers
+import ram.Ram
 import BitManipulation as bm
 
 // 8-Bit Loads
@@ -35,6 +37,17 @@ var loads16Bit = mapOf(
   0xE5 to Operation("PUSH HL", 0, 16, {r, m, _ ->
     m.writeByte(r.decrementAndGetSP(), bm.getMsb(r.HL))
     m.writeByte(r.decrementAndGetSP(), bm.getLsb(r.HL))
-  })
+  }),
+
+  0xF1 to Operation("POP AF", 0, 12, {r, m, _ -> r.AF = pop(r, m)}),
+  0xC1 to Operation("POP BC", 0, 12, {r, m, _ -> r.BC = pop(r, m)}),
+  0xD1 to Operation("POP DE", 0, 12, {r, m, _ -> r.DE = pop(r, m)}),
+  0xE1 to Operation("POP HL", 0, 12, {r, m, _ -> r.HL = pop(r, m)})
 
 )
+
+fun pop(r: Registers, m: Ram): Int {
+  val lsb = m.readByte(r.getAndIncrementSP())
+  val msb = m.readByte(r.getAndIncrementSP())
+  return bm.bytesToWord(msb, lsb)
+}