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| author | James Barnett <noreply@jamesbarnett.xyz> | 2018-07-17 21:01:26 +0100 |
|---|---|---|
| committer | James Barnett <noreply@jamesbarnett.xyz> | 2018-07-17 21:01:26 +0100 |
| commit | 7fd114712c1921cb03748d42deeb655f6b225cce (patch) | |
| tree | 9a79fc368fa50ce2778dd4513d982b82d4cee3b7 | |
| parent | 377d5637f618a11b0fca2d37063caa4c2284f85e (diff) | |
| download | KGB-7fd114712c1921cb03748d42deeb655f6b225cce.tar.xz KGB-7fd114712c1921cb03748d42deeb655f6b225cce.zip | |
Implement the last set of ops. RETs
| -rw-r--r-- | src/main/kotlin/cpu/Cpu.kt | 1 | ||||
| -rw-r--r-- | src/main/kotlin/cpu/opcodes/Returns.kt | 28 |
2 files changed, 29 insertions, 0 deletions
diff --git a/src/main/kotlin/cpu/Cpu.kt b/src/main/kotlin/cpu/Cpu.kt index 32fd39a..91150c4 100644 --- a/src/main/kotlin/cpu/Cpu.kt +++ b/src/main/kotlin/cpu/Cpu.kt @@ -21,6 +21,7 @@ class Cpu { stdCommandGroup.putAll(jumps) stdCommandGroup.putAll(calls) stdCommandGroup.putAll(restarts) + stdCommandGroup.putAll(returns) standardOpcodes = stdCommandGroup.toMap() val extCommandGroup: MutableMap<Int, Operation> = mutableMapOf() diff --git a/src/main/kotlin/cpu/opcodes/Returns.kt b/src/main/kotlin/cpu/opcodes/Returns.kt new file mode 100644 index 0000000..b78e2d6 --- /dev/null +++ b/src/main/kotlin/cpu/opcodes/Returns.kt @@ -0,0 +1,28 @@ +package cpu.opcodes + +import cpu.Operation +import cpu.Registers +import ram.Ram +import BitManipulation as bm + +val returns = mapOf( + + 0xC9 to Operation("RET", 0, 8, {r, m, _ -> ret(r, m)}), + + 0xC0 to Operation("RET NZ,nn", 0, 8, {r, m, _ -> if(r.getFlag(Registers.Flag.ZERO) == 0) ret(r, m)}), + 0xC8 to Operation("RET Z,nn", 0, 8, {r, m, _ -> if(r.getFlag(Registers.Flag.ZERO) == 1) ret(r, m)}), + 0xD0 to Operation("RET NC,nn", 0, 8, {r, m, _ -> if(r.getFlag(Registers.Flag.CARRY) == 0) ret(r, m)}), + 0xD8 to Operation("RET C,nn", 0, 8, {r, m, _ -> if(r.getFlag(Registers.Flag.CARRY) == 1) ret(r, m)}), + + // TODO - enable interrupts once added + 0xC9 to Operation("RET", 0, 8, {r, m, _ -> ret(r, m)}) + +) + +private fun ret(r: Registers, m: Ram) { + + val lsb = m.readByte(r.getAndIncrementSP()) + val msb = m.readByte(r.getAndIncrementSP()) + + r.PC = bm.bytesToWord(msb, lsb) +}
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